A central processor unit of a computer may communicate with peripheral devices, such as network adapters through an Input/Output (I/O) network. One type of I/O network is known and referred to as the InfiniBand® network. InfiniBand® which is a trademark of the InfiniBand® Trade Association is industry architecture for I/O communications. InfiniBand® architecture enables servers, remote storage and other networking devices, also called endnodes, to communicate concurrently through InfiniBand® architecture fabrics or subnets made of switches and routers that convey data packets to their destination, either within single or multiple subnets. A Subnet Manager Agent (SMA) of the InfiniBand® switch allows data packets received from one source endnode to be passed to a destination endnode within the same subnet. The Subnet Manager Agent configures the switches at the initialization of the network by sending commands to the Subnet Manager Agent. The configuration process includes implementing a routing table within each switch, referenced as the Forwarding Table or Forwarding Database (FDB).
Each destination endnode contains one or more channel adapters having one or more output ports. A unique address is assigned to each output port, known as the port's Local Identifier (LID). The LID address is related to the source endnode using a route field header of a data packet, namely the Local Route Header (LRH), to define its destination address. Each data packet has a unique Destination Local Identifier (DLID) assigned by the (SM) and corresponding to a 16-bit address of a switch output port through which the data packet is conveyed. A Forwarding Table located in a switch maps the DLIDs to the output ports. The Forwarding Database is arranged as a list of port blocks, each port block containing a list of destination output ports.
A complete description of the FDB and all previously defined elements of an InfiniBand® network may be found in the Infiniband® Architecture Specification Volume 1, Release 1.0.a, which is incorporated herein by reference.
To support high capacity switching, a switch may be implemented with several interconnected chips. A data packet arriving at an external input-port of such a switch may be routed internally through several levels of chips before arriving at its destination external output-port. These chips can either be separate switches from the point of view of the Subnet Manager, each with separate Subnet Manager Agent, or a combined switch with only one Subnet Manager Agent, greatly simplifying the management of such a switching fabric.
A multi-chip switch architecture implementation requires the maintenance of the complete routing path of each data packet regardless of the internal routing paths inside one or more switches.
Moreover, all the different constraints of priority, load balancing or Quality of Services (QoS) must be guaranteed as defined by the subnet manager.
The present invention offers a system and method to achieve these requirements.